The present invention relates generally to semiconductor memories, and more particularly to a layout structure for a memory array with semiconductor-on-insulator (SOI) devices.
While semiconductor memories continue to be designed in larger arrays, the individual cells and structures within them continue to decrease in size. Speed is increased and operating voltage is decreased as memory cells become smaller. Structures such as SOI and fin shaped field-effect-transistors (FinFETs) have emerged in recent years to reduce footprints of individual memory cells.
Besides the source, gate, and drain of a metal-oxide-semiconductor (MOS) transistor, the body also needs to be connected to a fixed potential. The body of a transistor could be viewed as the other side of the gate. The gate operates by charging the capacitance between the gate electrode and the active channel that is beneath the gate electrode. If the electrical potential of the body is changed, the bias applied to the gate electrode that is necessary to turn on the transistor will also change. This may result in a shift in the threshold voltage, VT, which is the designed gate voltage at which logic state switching occurs. For example, if the body is floating, it may accumulate charge and the threshold voltage may shift. A change of the threshold voltage of a transistor may cause the performance of a memory that contains the transistor unpredictable.
As more and more memories are formed with SOI transistors, connecting the bodies of the SOI transistors to a fixed potential becomes a challenging issue. As such, desirable in the art of memory designs are layout structures that allow a compact memory cell array formed with SOI transistors having their bodies properly connected to a fixed potential for preventing a threshold voltage shift caused by a floating body.